This invention relates to a charge-coupled device (CCD) and method of fabricating the same.
It is known to use a CCD array as a serialparallel-serial (SPS) analog shift register for high speed signal acquisition. For example, U.S. Pat. No. 4,725,748 issued Feb. 16, 1988 (Hayes et al.) discloses an SPS register using a four-phase CCD fabricated on a p-type silicon die having an n-type buried channel region.
An SPS analog shift register comprises an input serial register, an output serial register, and a parallel register that connects the input serial register to the output serial register. The parallel register is composed of multiple segments, each comprising a serial register, extending between the input register and the output register. An input signal is sampled at an input diode of the SPS shift register and consecutive samples are shifted through the input register. When the input register is full, the samples are shifted into respective segments of the parallel register, emptying the input register. The input register is filled and empties again, and as each group of samples is shifted into the parallel register the samples that were previously shifted into the parallel register are advanced by one step through the parallel register. Ultimately, each group of samples reaches the output register, and is shifted serially through the output register to an output node of the SPS shift register.
C. K. Kim, "Two-Phase Charge Coupled Linear Imaging Devices With Self-Aligned Implanted Barrier," International Electron Device Meeting, 1974, discloses an n-channel two-phase CCD in which alternate pairs of transfer gates are connected to two clock phases respectively. The gates are formed of polysilicon that has been deposited in two stages over a layer of gate oxide, so that each pair of gates comprises a lower level polysilicon gate and an upper level polysilicon gate. The upper level gates each have at least one edge region that partially overlaps an adjacent lower level gate. After the lower level polysilicon has been applied, and before the upper level polysilicon is applied, an implantation of a p-type dopant takes place. During this implantation, the lower level polysilicon serves as an implantation mask. The ions of the p-type dopant partially compensate the effect of the n-type dopant in the channel region. Accordingly, zones of n conductivity but having a lower net concentration of n-type dopant are formed in the channel region beneath the upper level gates, and form potential barriers between the n-type zones beneath the lower level gates. The width of the potential wells between the barriers depends on the width of the lower level gates.
As shown in FIG. 1A of the drawings, a two-phase CCD of the kind shown by Kim may be used in an SPS shift register. The direction of charge transfer is indicated by the arrow 12. The juncture between the input serial register 2 and one of the segments 4 of the parallel register is at the location of a potential well 6 of the serial register. In order to allow high speed operation of the register, it is desirable that this well be small, so that the distance traveled by an electron passing through the well is short. Referring to FIG. 1B, the size of the well 6 depends on the size of the lower level polysilicon gate 8 that overlies the well 6 and thus forms a mask with respect to the p-type implantation 10 that forms the barrier between wells. Accordingly, the time taken for an electron entering the well along the path A to pass through the well in the serial direction depends on the distance X and the time taken for such an electron to make a corner turn from the serial direction to the parallel direction and enter the parallel register depends on the distance Y.
The dopant that is generally used to form the p-type implant in a two-phase CCD of the kind shown by Kim is boron. Under certain processing conditions, boron will diffuse from the implant through the gate oxide under the lower level polysilicon, resulting in threshold shifts which may adversely affect the operation and manufacturability of the device.
It is known that in fabrication of integrated circuits, design rules for a given photolithographic process generally allow a lower minimum for the width of a space between conductor runs than for the width of conductor run.